Memory interface circuitry with improved timing margins

• Main Authors: CHONG YAN, NGUYEN KHAI, OOI EE MEI, NORDYKE WARREN, LU SEAN SHAU-TU
• Format: Patent
• Language: English
• Published: 20.10.2015
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; INFORMATION STORAGE; PHYSICS; PULSE TECHNIQUE; STATIC STORES

Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller.