Secure digital input/output low-power mode

• Main Authors: BERBESSOU DAVID, LACHWANI MANISH
• Format: Patent
• Language: English
• Published: 04.08.2015
• Subjects: CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; PHYSICS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

A low-power mode for interfaces, such as secure digital input/output (SDIO) interfaces, is described. The low-power mode provides significant power savings while allowing rapid resumption of data transfer on the interface. The SDIO low-power mode gates an SDIO clock and transitions the SDIO bus to a 1-bit mode. One line of the bus carries the 1-bit data while another line carries interrupts from an SDIO peripheral. Normal data transmission results in enabling the SDIO clock and setting the bus set to the 4-bit mode.