Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

• Main Authors: CHAWLA JASMEET S, JEZEWSKI CHRISTOPHER J
• Format: Patent
• Language: English
• Published: 09.06.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.