Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology

• Main Authors: IYER SUBRAMANIAN S, KOTHANDARAMAN CHANDRASEKHARAN, LEU DEREK H, KIRIHATA TOSHIAKI, MOY DAN
• Format: Patent
• Language: English
• Published: 05.05.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount ( VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.