Memory system comprising translation lookaside buffer and translation information buffer and related method of operation
A memory system comprises a translation lookaside buffer (TLB) configured to receive a virtual address and to search for a TLB entry matching the virtual address, and a translation information buffer (TIB) configured to be connected to the TLB and determine whether a physical address corresponding t...
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Main Author | |
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Format | Patent |
Language | English |
Published |
21.04.2015
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Subjects | |
Online Access | Get full text |
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Summary: | A memory system comprises a translation lookaside buffer (TLB) configured to receive a virtual address and to search for a TLB entry matching the virtual address, and a translation information buffer (TIB) configured to be connected to the TLB and determine whether a physical address corresponding to the virtual address falls into a continuous mapping area if the TLB entry matching the virtual address is not found. |
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Bibliography: | Application Number: US201113303395 |