Automatic generation of via definitions based on manufacturability
A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets f...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
14.04.2015
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device. |
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| AbstractList | A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device. |
| Author | SHARMA PUNEET YUAN CHI-MIN |
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| Notes | Application Number: US201314136057 |
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| RelatedCompanies | FREESCALE SEMICONDUCTOR, INC |
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| Snippet | A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical... |
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| SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| Title | Automatic generation of via definitions based on manufacturability |
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