Automatic generation of via definitions based on manufacturability

A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets f...

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Bibliographic Details
Main Authors YUAN CHI-MIN, SHARMA PUNEET
Format Patent
LanguageEnglish
Published 14.04.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device.
Bibliography:Application Number: US201314136057