Error correction and recovery in chained memory architectures

Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check a...

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Bibliographic Details
Main Author RESNICK DAVID R
Format Patent
LanguageEnglish
Published 14.04.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
SIGNALLING
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILARSIGNALS
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Summary:Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.
Bibliography:Application Number: US201414190637