Use of Frequency addition in a PLL control loop

• Main Authors: YAO HU JING, FORMAN DUSTIN DALE, MALLINSON A. MARTIN
• Format: Patent
• Language: English
• Published: 31.03.2015
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.