Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register

A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being wri...

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Bibliographic Details
Main Authors GLASS MARK CARPENTER, HARDAGE JAMES NOLAN, HARRIS GLEN ANDREW
Format Patent
LanguageEnglish
Published 03.03.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
Bibliography:Application Number: US201113312131