Synchronizing a translation lookaside buffer with an extended paging table

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas...

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Bibliographic Details
Main Authors NEIGER GILBERT, UHLIG RICHARD, RUST CAMRON, BENNETT STEVEN M, SANKARAN RAJESH M, SCHOENBERG SEBASTIAN, ANDERSON ANDREW V, RODGERS DION
Format Patent
LanguageEnglish
Published 03.02.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
Bibliography:Application Number: US201314070561