Associative memory

An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay a signal from t...

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Bibliographic Details
Main Authors SASAKI SEIRYU, KOIDE TETSUSHI, MATTAUSCH HANS JUERGEN, YASUDA MASAHIRO
Format Patent
LanguageEnglish
Published 20.01.2015
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay a signal from the NAND circuit 40 by longer delay time as the distance between reference data and search data is greater and oscillate the signal. Among R oscillation signals output from the distance/time conversion circuits DT1 to DTR, the earliest changing oscillation signal is detected as an oscillation signal for the Winner row.
Bibliography:Application Number: US201213466381