Content addressable memory continuous error detection with interleave parity

Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, wh...

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Bibliographic Details
Main Authors BROWNING CHRISTOPHER D, SWANSON CARL W, PRIEBE GORDON W, GROVER DAVID B
Format Patent
LanguageEnglish
Published 30.12.2014
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.
Bibliography:Application Number: US201213628616