Nearly buffer zone free layout methodology

The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first patt...

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Bibliographic Details
Main Authors LIU SZU-LIN, PENG YUNGOW, KANG PO-ZENG, HORNG JAW-JUINN
Format Patent
LanguageEnglish
Published 23.12.2014
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value. A difference between the first pattern density value and second pattern density value results in a density gradient at an edge of the array. Unit cells on the edge of the array which are impacted by a shape tolerance stress resulting from the density gradient are identified and reconfigured from a square shape aspect ratio to a rectangular shape aspect ratio with along axis of the unit cell oriented in a direction parallel to the variation induced shape tolerance stress to alleviate the variation.
Bibliography:Application Number: US201313745913