Variable resistance nonvolatile memory device and method of writing thereby
Provided is a variable resistance nonvolatile memory device that achieves, in multi-bit simultaneous writing for increasing a writing speed, writing with little variation caused by positions of memory cells in multi-bit simultaneous writing. The variable resistance nonvolatile memory device includes...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
02.12.2014
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Subjects | |
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Abstract | Provided is a variable resistance nonvolatile memory device that achieves, in multi-bit simultaneous writing for increasing a writing speed, writing with little variation caused by positions of memory cells in multi-bit simultaneous writing. The variable resistance nonvolatile memory device includes bit lines, word lines, memory cells, a first write circuit (e.g., a write circuit (60-0)), a second write circuit (e.g., a write circuit (60-k−1)), a first selection circuit (e.g., a selection circuit (S0-0)), a second selection circuit (e.g., a selection circuit (S0_k−1)), and a first word line drive circuit (a word line drive circuit (40-1)), wherein the first selection circuit (e.g., an NMOS transistor (TS0-0-0 to TS0-0_m−1) included in the selection circuit) has a greater ON resistance than the second selection circuit (e.g., an NMOS transistor (TS0_k−1-0 to TS0_k−1_m−1) included in the selection circuit) does. |
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AbstractList | Provided is a variable resistance nonvolatile memory device that achieves, in multi-bit simultaneous writing for increasing a writing speed, writing with little variation caused by positions of memory cells in multi-bit simultaneous writing. The variable resistance nonvolatile memory device includes bit lines, word lines, memory cells, a first write circuit (e.g., a write circuit (60-0)), a second write circuit (e.g., a write circuit (60-k−1)), a first selection circuit (e.g., a selection circuit (S0-0)), a second selection circuit (e.g., a selection circuit (S0_k−1)), and a first word line drive circuit (a word line drive circuit (40-1)), wherein the first selection circuit (e.g., an NMOS transistor (TS0-0-0 to TS0-0_m−1) included in the selection circuit) has a greater ON resistance than the second selection circuit (e.g., an NMOS transistor (TS0_k−1-0 to TS0_k−1_m−1) included in the selection circuit) does. |
Author | AZUMA RYOTARO KAWAHARA AKIFUMI SHIMAKAWA KAZUHIKO TANABE KOUHEI |
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Snippet | Provided is a variable resistance nonvolatile memory device that achieves, in multi-bit simultaneous writing for increasing a writing speed, writing with... |
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Title | Variable resistance nonvolatile memory device and method of writing thereby |
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