Method and circuit for suppressing bias current and reducing power loss
A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, t...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
02.12.2014
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Subjects | |
Online Access | Get full text |
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Summary: | A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, the current suppression circuit applies a voltage to the node in response to a heavy load. In another operating mode, the current suppression circuit lowers the voltage at the node in response to a light load or no load. Lowering the voltage at the node decreases the flow of bias current through the circuit element thereby lowering power loss. |
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Bibliography: | Application Number: US200913264153 |