Reducing gate height variance during semiconductor device formation
In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are r...
Saved in:
Main Authors | , , , , , |
---|---|
Format | Patent |
Language | English |
Published |
02.12.2014
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity. |
---|---|
Bibliography: | Application Number: US201313738270 |