Processor and cache arrangement with selective caching between first-level and second-level caches

Approaches for caching addressable items in a multiprocessor system. Instructions are cached in a plurality of first-level instruction caches respectively coupled to a plurality of processors of the multiprocessor system. First-type data items are cached in a plurality of first-level data caches res...

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Bibliographic Details
Main Authors MASON JEFFREY M, BENNETT DAVID W
Format Patent
LanguageEnglish
Published 21.10.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Approaches for caching addressable items in a multiprocessor system. Instructions are cached in a plurality of first-level instruction caches respectively coupled to a plurality of processors of the multiprocessor system. First-type data items are cached in a plurality of first-level data caches respectively coupled to the plurality of processors. Second-type data items are cached in a second-level cache and are not cached in any of the plurality of first-level data caches.
Bibliography:Application Number: US201113196398