Flip chip assembly process for ultra thin substrate and package on package assembly

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the s...

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Main Authors LIM SIH FEI, LOKE MUN LEONG, ONG KANG EU, RUDGE A. VETHANAYAGAM, MONG WENG KHOON, LIM BOK SIM, ONE TEAN WEE
Format Patent
LanguageEnglish
Published 30.09.2014
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Abstract In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
AbstractList In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
Author LIM SIH FEI
ONG KANG EU
RUDGE A. VETHANAYAGAM
LIM BOK SIM
LOKE MUN LEONG
MONG WENG KHOON
ONE TEAN WEE
Author_xml – fullname: LIM SIH FEI
– fullname: LOKE MUN LEONG
– fullname: ONG KANG EU
– fullname: RUDGE A. VETHANAYAGAM
– fullname: MONG WENG KHOON
– fullname: LIM BOK SIM
– fullname: ONE TEAN WEE
BookMark eNrjYmDJy89L5WQIdsvJLFBIzgASicXFqblJOZUKBUX5yanFxQpp-UUKpTklRYkKJRmZeQrFpUnFQE5JqkJiXopCQWJydmJ6qkJ-HpwJM4CHgTUtMac4lRdKczMouLmGOHvophbkx6cWA5Wn5qWWxIcGW1iYmBubWTgZGROhBAASsDn3
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US8847368B2
GroupedDBID EVB
ID FETCH-epo_espacenet_US8847368B23
IEDL.DBID EVB
IngestDate Fri Jul 19 15:03:33 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US8847368B23
Notes Application Number: US201213600547
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140930&DB=EPODOC&CC=US&NR=8847368B2
ParticipantIDs epo_espacenet_US8847368B2
PublicationCentury 2000
PublicationDate 20140930
PublicationDateYYYYMMDD 2014-09-30
PublicationDate_xml – month: 09
  year: 2014
  text: 20140930
  day: 30
PublicationDecade 2010
PublicationYear 2014
RelatedCompanies LIM SIH FEI
ONG KANG EU
RUDGE A. VETHANAYAGAM
LIM BOK SIM
INTEL CORPORATION
LOKE MUN LEONG
MONG WENG KHOON
ONE TEAN WEE
RelatedCompanies_xml – name: ONG KANG EU
– name: ONE TEAN WEE
– name: RUDGE A. VETHANAYAGAM
– name: LIM BOK SIM
– name: LIM SIH FEI
– name: MONG WENG KHOON
– name: LOKE MUN LEONG
– name: INTEL CORPORATION
Score 2.958992
Snippet In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Flip chip assembly process for ultra thin substrate and package on package assembly
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140930&DB=EPODOC&locale=&CC=US&NR=8847368B2
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFfWmVbG-2IPkFmyb9yEIeVGEPjCt9FY26YaGxk1oUsR_72z60ItelmEXhuzAfPttdvZbgKdYNwzKFlRGtkpl1YximVK0IrWXKL1EM2IqTnQHQ70_VV9n2qwB6f4uTK0T-lmLI2JGxZjvVY3Xxc9PLK-urSyfoxS78pdgYnvSbncs1JuUjuQ5tj8eeSNXcl17GkrDN9tEFFZ000G0PhIsWsjs---OuJRS_F5RgnM4HqMzXl1Ag_EWnLr7h9dacDLYnXejuUu98hLCIEsLEi-xQb7LPqLsixTbKn-CxJNssmpNSbVMOSkRDGrRWUL5guD8VggaJOcHc-_gCkjgT9y-jF83P0RiPg0P81Cuoclzzm6AJMj6ugK0rFhVLWpanUjrJl1mmYxqRm_Rhvafbm7_GbuDMxHSbXXEPTSr9YY94BJcRY918L4BxSWNGg
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dT8IwEL8QNOKbokb87IPZ2yLsg20Piwkby1S-ImB4W7rRhQUsC4wY_3tvBaYv-tJc2uTSu-R-vetdrwAPUdMwKJtSGb1VKmtmGMmUIhVqSqwqsW5ENM_odntNf6y9TPRJCZL9WxjRJ_RTNEdEi4rQ3jOB1-nPJZYraivXj2GCU8snb2S70i46zrs3qXXJbdntQd_tO5Lj2OOh1HuzTURhtWm2EK0PDIwIRaT03sofpaS_TxTvBA4HyIxnp1BivAoVZ__xWhWOurt8N5I701ufwdBbJCmJZjigv8s-wsUXSbdV_gQdT7JZZCtKslnCyRrBQDSdJZRPCco3R9AgS16QewbnQLz2yPFl3F1QaCIYDws51Aso8yVnl0Bi9PoaOWhZkaZZ1LTqod6IG8wyGdUNZVqD2p9srv5Zu4eKP-p2gs5z7_UajnP1bislbqCcrTbsFo_jLLwTivwGg36QBA
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Flip+chip+assembly+process+for+ultra+thin+substrate+and+package+on+package+assembly&rft.inventor=LIM+SIH+FEI&rft.inventor=LOKE+MUN+LEONG&rft.inventor=ONG+KANG+EU&rft.inventor=RUDGE+A.+VETHANAYAGAM&rft.inventor=MONG+WENG+KHOON&rft.inventor=LIM+BOK+SIM&rft.inventor=ONE+TEAN+WEE&rft.date=2014-09-30&rft.externalDBID=B2&rft.externalDocID=US8847368B2