Method of generating technology file for integrated circuit design tools

A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file prepara...

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Bibliographic Details
Main Authors HOU CLIFF, YAO CHIH-TSUNG, YEH CHENG-HUNG, CHANG GWAN SIN
Format Patent
LanguageEnglish
Published 02.09.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.
Bibliography:Application Number: US20070966570