Semiconductor memory device suitable for interconnection in a ring topology

A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for r...

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Bibliographic Details
Main Authors OH HAKJUNE, KIM JIN-KI
Format Patent
LanguageEnglish
Published 02.09.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.
Bibliography:Application Number: US20080141384