Fabrication method for embedded magnetic memory

A wafer has a memory area and a logic area and a topmost metal contact layer on the surface covered with dielectric and etch stop layers. In the memory area, vias are opened through the dielectric and etch stop layers to topmost metal contact layer. In the logic area, evenly distributed dummy fill p...

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Bibliographic Details
Main Authors HUANG KENLIN, ZHONG TOM, TORNG CHYU-JIUH
Format Patent
LanguageEnglish
Published 08.07.2014
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A wafer has a memory area and a logic area and a topmost metal contact layer on the surface covered with dielectric and etch stop layers. In the memory area, vias are opened through the dielectric and etch stop layers to topmost metal contact layer. In the logic area, evenly distributed dummy fill patterns are opened through a portion of the dielectric and etch stop layers. These are filled with a metal layer and planarized, forming a flat wafer surface. MTJ elements in the memory area and dummy elements in the logic area are formed on the flat surface. The dummy MTJ elements and fill patterns are etched away in the logic area. Metal connections are formed to the topmost metal contact layer in the logic area and top lead connections to MTJ elements are formed in the memory area.
Bibliography:Application Number: US201313766990