System for generating clock signal

• Main Authors: GUPTA NITI, GUPTA SUNNY, SINHA SAMAKSH
• Format: Patent
• Language: English
• Published: 24.06.2014
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.