Memory link power management

Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating c...

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Bibliographic Details
Main Authors GANESAN BASKARAN, SUGUMAR SURESH, THOMAS TESSIL, NAIK VIJAYANAND
Format Patent
LanguageEnglish
Published 03.06.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating conditions. Embodiments of the invention similarly describe exiting low power states for memory links and various components of a memory subsystem upon detecting certain operating conditions. Embodiments of the invention may detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards a memory unit, a processor core executing a processor low-power mode, and a processor socket executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit and various components of the memory subsystem.
Bibliography:Application Number: US201113206923