Non-overlapping clock generator circuit and method

• Main Author: GARRITY DOUGLAS A
• Format: Patent
• Language: English
• Published: 27.05.2014
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; PULSE TECHNIQUE

A non-overlapping clock generator circuit supplies clock signals to a stage of a pipelined ADC, which includes parallel switched capacitor circuitry. The non-overlapping clock generator circuit includes: a first trigger generation circuit that generates first and second trigger signals; a second trigger generation circuit that generates third and fourth trigger signals; a first clock generation branch that receives the first, second and fourth trigger signals and generates first sampling cycle and delayed sampling cycle clock signals; a second clock generation branch that receives the first, second and third trigger signals and generates second sampling cycle and delayed sampling cycle clock signals; a third clock generation branch that receives the second trigger signal and generates first gain cycle and delayed gain cycle clock signals; and a fourth clock generation branch that receives the first trigger signal and generates second gain cycle and delayed gain cycle clock signals.