Method for making embedded cost-efficient SONOS non-volatile memory

• Main Authors: ROIZIN YAKOV, PIKHAY EVGENY, HEIMAN ALEXEY, GUTMAN MICHA
• Format: Patent
• Language: English
• Published: 13.05.2014
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell production method for CMOS ICs, where the CEONOS NVM cell requires two or three additional masks, but can otherwise be formed using the same standard CMOS flow processes used to form NMOS transistors. A first additional mask is used to form an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data (i.e., trapped charges). A second additional mask is used to perform drain engineering, including a special pocket implant and LDD extensions, which facilitates program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).