Thin film transistor array panel and method for manufacturing the same
A manufacturing method of a thin film transistor array panel includes forming a gate line, forming a gate insulating layer on the gate line, forming a data line including a drain electrode on the gate insulating layer, forming a passivation layer on the gate insulating layer, the data line, and the...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
14.01.2014
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Subjects | |
Online Access | Get full text |
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Summary: | A manufacturing method of a thin film transistor array panel includes forming a gate line, forming a gate insulating layer on the gate line, forming a data line including a drain electrode on the gate insulating layer, forming a passivation layer on the gate insulating layer, the data line, and the drain electrode, forming a negative photosensitive organic layer on the passivation layer, heat treating the negative photosensitive organic layer to form an insulating layer including a first portion, and a second portion that is thinner than the first portion, and forming a pixel electrode, a first contact assistant, and a second contact assistant on the insulating layer. The pixel electrode is disposed on the first portion, the first and second contact assistants are disposed on the second portion, and the thickness of the second portion is less than about 1.5 micrometers (mum). |
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Bibliography: | Application Number: US201313875494 |