Method and circuitry for debugging a power-gated circuit

Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in...

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Bibliographic Details
Main Authors RENTSCHLER ERIC, BONDALAPATI KIRAN, SCHREIBER JEREMY, TSIEN BENJAMIN, HUANG HAO, HUGHES WILLIAM A, GRENAT AARON J
Format Patent
LanguageEnglish
Published 26.11.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.
Bibliography:Application Number: US201113184982