Data process for E-beam lithography

The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray ma...

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Bibliographic Details
Main Authors CHEN JENG-HORNG, CHEN PEI-SHIANG, WANG SHIHI, CHEN CHENG-HUNG
Format Patent
LanguageEnglish
Published 22.10.2013
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
AUXILIARY PROCESSES IN PHOTOGRAPHY
CINEMATOGRAPHY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHIC PROCESSES, e.g. CINE, X-RAY, COLOUR,STEREO-PHOTOGRAPHIC PROCESSES
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHOTOSENSITIVE MATERIALS FOR PHOTOGRAPHIC PURPOSES
PHYSICS
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Summary:The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.
Bibliography:Application Number: US201213487850