Generation of cache architecture from a high-level language description

Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating in...

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Bibliographic Details
Main Authors MASON JEFFREY M, WENZL LAUREN B, BENNETT DAVID W, DIMOND ROBERT G, SUNDARARAJAN PRASANNA
Format Patent
LanguageEnglish
Published 25.06.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.
Bibliography:Application Number: US20080009272