Semiconductor device having a nonvolatile memory cell with a cap insulating film formed over a selection gate electrode
To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conduc...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
01.01.2013
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode. |
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Bibliography: | Application Number: US20100699731 |