Semiconductor memory apparatus and test method thereof

A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output on...

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Bibliographic Details
Main Authors YUN TAE SIK, BYEON SANG JIN, SHIN SANG HOON, LEE HYUNG DONG, CHOI JUN GI
Format Patent
LanguageEnglish
Published 30.10.2012
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.
Bibliography:Application Number: US20100948874