3-dimensional device design layout

A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a...

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Bibliographic Details
Main Authors CHUANG HARRY, THEI KONG-BENG, SHEN GARY, YAO CHIH-TSUNG, CHENG CHUNG LONG, LIANG MONG SONG, CHUNG SHENGN, CHANG GWAN SIN, KAO JUNG-HUI
Format Patent
LanguageEnglish
Published 09.10.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
Bibliography:Application Number: US20070833119