Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics

• Main Authors: JANSEN JOHN G, CHEN CE, MOINIAN SHAHRIAR, KAO CHI-YI
• Format: Patent
• Language: English
• Published: 09.10.2012
• Subjects: ELECTRICITY

An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.