Stacked semiconductor package

A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first surface and a second surface facing away from the first surface, first bonding pads disposed on the first surface, and through-electrodes electrically connected with the first bond...

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Bibliographic Details
Main Author JO JAE HO
Format Patent
LanguageEnglish
Published 28.08.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first surface and a second surface facing away from the first surface, first bonding pads disposed on the first surface, and through-electrodes electrically connected with the first bonding pads The through-electrodes pass through the first and second surfaces of the first chip and extend from the second surface. A second semiconductor package has a through-holes defined therein into which the through-electrodes are inserted and second bonding pads electrically connected with the through-electrodes.
Bibliography:Application Number: US20090605444