L2 ECC implementation

One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typica...

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Bibliographic Details
Main Authors HOLMQVIST PETER B, MARCHAND PATRICK R, MEHRA KARAN, LYNCH GEORGE R, GLASCO DAVID B, ROBERTS JAMES
Format Patent
LanguageEnglish
Published 10.04.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.
Bibliography:Application Number: US20080202161