Method and system for implementing pattern matching of integrated circuit features using voronoi diagrams

A method for implementing pattern matching of integrated circuit features includes computing Voronoi edge regions for both a reference configuration and a search space of an integrated circuit design to be searched and presenting the computed Voronoi edge regions of the reference configuration to a...

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Bibliographic Details
Main Author MONKOWSKI MICHAEL D
Format Patent
LanguageEnglish
Published 21.02.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for implementing pattern matching of integrated circuit features includes computing Voronoi edge regions for both a reference configuration and a search space of an integrated circuit design to be searched and presenting the computed Voronoi edge regions of the reference configuration to a user; receiving one or more selected bisectors of the Voronoi computed reference configuration from the user, indicative of user identified salient regions of design shapes and/or corners to be searched, so as to define one or more search elements, wherein a search element comprises a given bisector and a pair of Voronoi edge regions bounded thereby; constructing a search pattern from the one or more search elements defined from the reference configuration; examining the search space for matching sequences with respect to the search pattern; and highlighting resulting matching patterns in the search space for the user.
Bibliography:Application Number: US20080137616