Concurrent multiple-dimension word-addressable memory architecture

An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimensio...

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Bibliographic Details
Main Authors CHAIYAKUL VIRAPHOL, CHEN CHIHTUNG, KANG INYUP
Format Patent
LanguageEnglish
Published 21.02.2012
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
Bibliography:Application Number: US20070767639