Shallow extension regions having abrupt extension junctions

A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging fro...

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Main Authors LEE KAM-LEUNG, RONSHEIM PAUL A
Format Patent
LanguageEnglish
Published 14.02.2012
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Abstract A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.
AbstractList A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.
Author RONSHEIM PAUL A
LEE KAM-LEUNG
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RONSHEIM PAUL A
LEE KAM-LEUNG
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Snippet A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Shallow extension regions having abrupt extension junctions
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