Shallow extension regions having abrupt extension junctions

A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging fro...

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Bibliographic Details
Main Authors LEE KAM-LEUNG, RONSHEIM PAUL A
Format Patent
LanguageEnglish
Published 14.02.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.
Bibliography:Application Number: US20090491819