Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer

A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the S...

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Bibliographic Details
Main Authors ENDO AKIHIKO, MATSUMOTO KOJI, NINOMIYA MASAHARU, HORA TOMOYUKI, MORITA ETSUROU
Format Patent
LanguageEnglish
Published 07.02.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.
Bibliography:Application Number: US20070649943