Method and system for verifying power-optimized electronic designs using equivalency checking

• Main Authors: NARAYANAN SRIDHAR, SUBRAMANIAN SRIDHAR, MANOVIT CHAIYASIT
• Format: Patent
• Language: English
• Published: 17.01.2012
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications. The equivalency between the golden design and the power optimized design can then be verified by checking the golden design and the first design transformation, and then by checking between each pair of the plurality of intermediate design transformations, and finally by checking the last design transformation and the power optimized design.