SRAM leakage reduction circuit

A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vth across the memory ce...

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Bibliographic Details
Main Authors TOOHER MICHAEL, ZAMPAGLIONE MICHAEL ANTHONY
Format Patent
LanguageEnglish
Published 13.12.2011
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.
Bibliography:Application Number: US20100705345