Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same

• Main Authors: NAKAMURA HIROSHI, HOSONO KOJI, NAKANO TAKESHI
• Format: Patent
• Language: English
• Published: 13.12.2011
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.