Semiconductor integrated circuit
During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase compa...
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Main Author | |
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Format | Patent |
Language | English |
Published |
18.10.2011
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Subjects | |
Online Access | Get full text |
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Summary: | During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. |
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Bibliography: | Application Number: US20100890253 |