Techniques for integrated circuit clock management using multiple clock generators

A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock s...

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Bibliographic Details
Main Authors KWAN BILL K. C, BAILEY DANIEL W, EATON CRAIG
Format Patent
LanguageEnglish
Published 06.09.2011
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator (404) is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator (406) is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.
Bibliography:Application Number: US20070750290