Method and apparatus for a zero voltage processor sleep state

• Main Authors: ALLAREY JOSE, JAHAGIRDAR SANJEEV
• Format: Patent
• Language: English
• Published: 31.05.2011
• Subjects: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS; BLASTING; CALCULATING; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER; COMBUSTION ENGINES; COMPUTING; CONTROL OR REGULATION THEREOF; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS; GENERATION; HEATING; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS; IGNITION, OTHER THAN COMPRESSION IGNITION, FORINTERNAL-COMBUSTION ENGINES; INFORMATION STORAGE; LIGHTING; MEASURING; MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUIDLEVEL; MECHANICAL ENGINEERING; METERING BY VOLUME; PHYSICS; STATIC STORES; SYSTEMS FOR STORING ELECTRIC ENERGY; TESTING; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES; WEAPONS

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.