Digital delay locked loop implementation for precise control of timing signals

• Main Authors: MAHAJAN RAJ, MENON RAGHAVAN
• Format: Patent
• Language: English
• Published: 22.03.2011
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; INFORMATION STORAGE; PHYSICS; STATIC STORES

An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay...