Digital delay locked loop implementation for precise control of timing signals

An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay...

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Bibliographic Details
Main Authors MAHAJAN RAJ, MENON RAGHAVAN
Format Patent
LanguageEnglish
Published 22.03.2011
Subjects
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