Digital delay locked loop implementation for precise control of timing signals
An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
22.03.2011
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Subjects | |
Online Access | Get full text |
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Summary: | An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay line and a fine delay line. The coarse delay line delays a signal by a fixed large amount and the fine delay line introduces a smaller precise delay. The delay control FSM adjusts the delay to keep the output signal of the DLL synchronized with the input. The adjustment is averaged over a range of cycle periods in order to avoid adjusting the edges of signal waveform constantly. The low pass filter at the output minimizes the jitter in the output signal. |
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Bibliography: | Application Number: US20080346854 |