Etch residue reduction by ash methodology

Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity...

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Bibliographic Details
Main Authors JACQUES JEANNETTE MICHELLE, RAMAPPA DEEPAK A
Format Patent
LanguageEnglish
Published 22.03.2011
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.
Bibliography:Application Number: US20070965972